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1 characteristics subject to change without notice 2055 4.1 03/27 /09 smh4812 summit microelectronics, inc. ?summit microelectronics, inc., 2000 ? 757 n. mary ave. sunnyvale, ca 94085 phone 408-523-1000 fax 408-523-1266 www.summitmicro.com preliminary distributed power hot-swap controller features simplified application drawing ! ! ! ! ! soft starts main power supply on card insertion or system power up ! ! ! ! ! senses card insertion via short pins or ejector switches ! ! ! ! ! master enable to allow system control of power up or down " " " " " can be used as a temperature sense input ! ! ! ! ! programmable independent controls of a dc/dc converter " " " " " not enabled until host supply fully soft started " " " " " programmable time delay " " " " " available input to hold off dependant enables until conditions are satisfied ! ! ! ! ! highly programmable circuit breaker " " " " " programmable quick-trip tm values " " " " " programmable current limiting " " " " " programmable duty cycle times " " " " " programmable over-current filter ! ! ! ! ! programmable host voltage fault monitoring " " " " " programmable under-voltage hysteresis " " " " " programmable uv/ov voltage filter " " " " " programmable fault mode: latched or duty cycle ! ! ! ! ! programmable forced shutdown timer ! ! ! ! ! 2.5v and 5.0v reference outputs " " " " " eliminates the need for other primary volt- ages " " " " " easy expansion of external monitor func- tions ! ! ! ! ! supply range +20vdc to > +500vdc vdd vss cbsense pd1# pd2# uv ov 2.5vref pg2# 5.0vref 2055 sad 1.1 0v ?48v vgate pin detect pin detect dc/dc smh4812 fault# enpg disable/enable fs#
2 smh4812 2055 4.1 03/27 /09 summit microelectronics, inc. preliminary functional block diagram programm- able delay programm- able delay + ? + ? + ? programmable quick response ref. voltage 50mv duty cycle timer filter + ? + ? 5v 2.5v 12v vgate sense + ? vdd vss cbsense en/ts pd1# pd2# uv ov enpg 2.5vref pg# drain sense vgate fault# 5.0vref 12vref 2055 bd 3.0 programm- able shutdown timer fs# 16 3 1 4 10 8 5 9 7 2 6 11 15 13 12 14 50k ? ? ? ? the smh4812 is designed to control hot swapping of plug- in cards operating from a single supply, which can have an output range from 20v to 500v. the smh4812 hot-swap controller provides under-voltage and over-voltage moni- toring of the host power supply, it drives an external power mosfet switch that connects the supply to the load, and it protects against over-current conditions that might dis- rupt the host supply. when the input and output voltages to the smh4812 controller are within specification it pro- description vides a power good logic output that may be used to enable a dc-dc converter. additional features of the device include: temperature sense or master enable input, 2.5v and 5v reference outputs for expanding moni- tor functions, two pin-detect enable inputs for fault protec- tion, and duty-cycle or latched over-current protection modes. all of these features can be programmed by the factory according to the user's requirements.
3 2055 4.1 03/27 /09 smh4812 summit microelectronics, inc. preliminary pin configuration pin descriptions drain sense (1) the drain sense input monitors the voltage at the drain of the external power mosfet switch with respect to v ss . an internal 10a source pulls the drain sense signal towards the 5v reference level. drain sense must be held below 2.5v to enable the pg outputs. en/ts (3) the enable/temperature sense input is the master en- able input. if en/ts is less than 2.5v, vgate will be disabled. this pin has an internal 200kw pull-up to 5v. pd1#, pd2# (4, 5) these are logic level active low inputs that can optionally be employed to enable vgate and the pg outputs when they are at v ss . these pins each have an internal 50kw pull-up to 5v. cbsense (7) the circuit breaker sense input is used to detect over- current conditions across an external, low value sense resistor (r s ) tied in series with the power mosfet. a voltage drop of greater than 50mv across the resistor for longer than t cbd will trip the circuit breaker. a program- mable quick-trip sense point is also available. uv (9) the uv pin is used as an under-voltage supply monitor, typically in conjunction with an external resistor ladder. vgate will be disabled if uv is less than 2.5v. program- mable internal hysteresis is available on the uv input, adjustable in increments of 62.5mv. also available is a filter delay on the uv input. ov (10) the ov pin is used as an over-voltage supply monitor, typically in conjunction with an external resistor ladder. vgate will be disabled if ov is greater than 2.5v. a filter delay is available on the ov input. vgate (2) the vgate output activates an external power mosfet switch. this signal supplies a constant current output (100a typical), which allows easy adjustment of the mosfet turn on slew rate. fault # (6) fault# is an open-drain, active-low output that indicates the fault status of the device. 5vref (11) this is a precision 5v output reference voltage that may be used to expand the logic input functions on the smh4812. the reference output is with respect to v ss . 2.5vref (12) this is a precision 2.5v output reference voltage that may be used to expand the logic input functions on the smh4812. the reference output is with respect to v ss . fs# (13) the forced shutdown (fs#) pin is an active low input that causes vgate and pg outputs to be shut down at any time after an internal hold-off timer has expired. the hold- off timer allows supervisory circuits on the secondary side (which are not powered up initially) to control shut down of the smh4812 via an opto-isolator. this input has no pull- up resistor. drain sense vgate en/ts pd1# pd2# fault# cbsense v ss v dd pg# enpg fs# 2.5v ref 5v ref ov uv 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 2055 pcon 2.0
4 smh4812 2055 4.1 03/27 /09 summit microelectronics, inc. preliminary enpg (14) the enpg input controls the pg# output. when enpg is pulled low the pg# output is immediately placed in a high impedance state. if enpg is driven high then the pg# output will immediately be driven low. pg# (15) pg# is an open-drain, active-low output with no internal pull-up resistor. it can be used to switch a load or enable a dc/dc converter. pg# is enabled immediately after vgate reaches v dd ? v gt and the drain sense voltage is less than 2.5v. voltage on these pins cannot exceed 12v, as referenced to v ss. v dd (16) v dd is the positive supply connection. an internal shunt regulator connected between v dd and v ss develops ap- proximately 12v that supplies the smh4812. a resistor must be placed in series with the v dd pin to limit the regulator current (rd in the application illustrations). v ss (8) v ss is connected to the negative side of the supply.
5 2055 4.1 03/27 /09 9smh4812 summit microelectronics, inc. preliminary 2055 prog table * comment stresses listed under absolute maximum ratings may cause perma- nent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. temperature under bias ...................... ? 55 c to 125 c storage temperature ........................... ? 65 c to 150 c lead solder temperature (10 secs) ................... 300 c terminal voltage with respect to v ss : v dd ................................. ? 0.5v to v dd ov, uv, drain sense, fs#, cbsense ..... ? 0.5v to v dd +0.5v pd1#, pd2#, enpg, en/ts ......... 10v fault#, pg# ........ ? 0.5v to v dd +0.5v vgate ................................ v dd +0.5v absolute maximum ratings* ac operating characteristics l o b m y sn o i t p i r c s e d. n i m. p y t. x a ms t i n u t d b c y a l e d r e k a e r b t i u c r i c v m 0 5 e l b a m m a r g o r p ) r e t l i f ( 5s 0 5 * s 0 5 1s 0 0 4s t d g v y a l e d d o o g r e w o p e l b a m m a r g o r p 0 5s 0 5 2s 0 0 5s 0 0 5 1s 5 * s m 0 2s m 0 8s m 0 6 1s m t n d t h s t s f v o t t l u a f m o r f y a l e d n w o d t u h s t s a f e t a g f f o0 0 2s n t c y c e m i t e l c y c r e k a e r b t i u c r i c5 . 2s t t s r b c b c t e s e r h t d i w e s l u p0 0 2s n t f v u p r e t l i f e g a t l o v - r e d n u e l b a m m a r g o r p f f o * ? 5s m 0 8s m 0 6 1s m t d d p t c e t e d n i p e l b a m m a r g o r p 5 . 0s m 5s m 0 8 * s m 0 6 1s m * = default value
6 smh4812 2055 4.1 03/27 /09 summit microelectronics, inc. preliminary dc operating characteristics ( over recommended operating conditions; voltages are relative to v ss , except v gt ) 2055 elect table l o b m y sr e t e m a r a ps n o i t i d n o c. n i m. p y t. x a ms t i n u v d d e g a t l o v y l p p u si d d a m 3 =1 12 13 1v v 5 f e r t u p t u o e c n e r e f e r v 5i d d a m 3 =5 7 . 40 0 . 55 2 . 5v i 5 d a o l t n e r r u c t u p t u o e c n e r e f e r v 5i d d a m 3 =1 ? 1a m v 5 . 2 f e r t u p t u o e c n e r e f e r v 5 . 2i d d ) 1 ( a m 3 =5 7 4 . 20 0 5 . 25 2 5 . 2v i 5 . 2 d a o l t n e r r u c t u p t u o e c n e r e f e r v 5 . 2i d d a m 3 =2 . 0 ? 1a m i d d t n e r r u c y l p p u s r e w o p 0 1a m v v u d l o h s e r h t e g a t l o v - r e d n ui d d ) 1 ( a m 3 =5 7 4 . 20 0 5 . 25 2 5 . 2v v t s y h v u s i s e r e t s y h e g a t l o v - r e d n ui d d a m 3 =3 6v m v v o d l o h s e r h t e g a t l o v - r e v oi d d ) 1 ( a m 3 =5 7 4 . 20 0 5 . 25 2 5 . 2v v t s y h v o s i s e r e t s y h e g a t l o v - r e v oi d d a m 3 =0 1v m v e t a g v e t a g e g a t l o v t u p t u o v d d v i e t a g v e t a g t u p t u o t n e r r u c0 0 1a v e s n e s d l o h s e r h t e s n e s n i a r di d d ) 1 ( a m 3 =5 7 4 . 20 0 5 . 25 2 5 . 2v i e s n e s t u p t u o t n e r r u c e s n e s n i a r dv e s n e s v = s s ) 1 (9 0 11 1a v b c d l o h s e r h t r e k a e r b t i u c r i ci d d a m 3 =0 40 50 6v m v b c q t i u c r i c p i r t k c i u q e l b a m m a r g o r p d l o h s e r h t r e k a e r b 0 0 2v m 0 0 1v m 0 6v m f f o ? v s t n e d l o h s e r h t s t / n ei d d ) 1 ( a m 3 =5 7 4 . 20 0 5 . 25 2 5 . 2v v t s y h s t n e s i s e r e t s y h s t / n ei d d a m 3 =0 1v m v h i g p n e : e g a t l o v h g i h t u p n i 3v 5 f e r v v l i 02v v l o # t l u a f : e g a t l o v w o l t u p t u oi l o a m 3 =0 4 . 0v # g p : e g a t l o v w o l t u p t u oi l o a m 3 =0 4 . 0v i l i s t / n e , # 2 d p , # 1 d p : t n e r r u c t u p n iv l i v = s s 0 0 1a v t g d l o h s e r h t e t a g7 . 08 . 10 . 3v (1) ta = 25 o c. recommended operating conditions temperature ? 40 c to 85 c.
7 2055 4.1 03/27 /09 smh4812 summit microelectronics, inc. preliminary functional description general operation the smh4812 is an integrated power controller for hot swappable add-in cards. the device operates from a wide supply range and generates the signals necessary to drive an isolated output dc/dc converter. as a typical add-in board is inserted into the powered backplane physical connections must first be made with the chassis to dis- charge any electrostatic voltage potentials. the board then contacts the long pins on the backplane that provide power and ground. as soon as power is applied the device starts up, but does not immediately apply power to the output load. under-voltage and over-voltage circuits inside the controller check to see that the input voltage is within a user-specified range, and pin detection signals determine whether the card is seated properly. these requirements must be met for a pin detect delay period of t pdd , after which time the hot-swap controller enables vgate to turn on the external power mosfet switch. the vgate output is current limited to i vgate , allowing the slew rate to be easily modified using external passive components. during the controlled turn-on period the v ds of the mosfet is monitored by the drain sense input. when drain sense drops below 2.5v, and vgate gets above v dd ? v gt , the power good output can begin turning on the dc/dc controller. the power good enable input may be used to activate or deactivate the output load. steady state operation is maintained as long as all condi- tions are normal. any of the following events may cause the device to disable the dc/dc controller by shutting down the power mosfet: an under-voltage or over- voltage condition on the host power supply; an over- current event detected on the cbsense input; a failure of the power mosfet sensed via the drain sense pin; the pin detect signals becoming invalid; the master enable (en/ts) falling below 2.5v; the fs# input being driven low by events on the secondary side of the dc/dc controller. the smh4812 may be configured so that after any of these events occur the vgate output shuts off and either latches into an off state or recycles power after a cooling down period, t cyc . powering v dd the smh4812 contains a shunt regulator on the v dd pin that prevents the voltage from exceeding 12v. it is necessary to use a dropper resistor (r d ) between the host power supply and the v dd pin in order to limit current into the device and prevent possible damage. the dropper resistor allows the device to operate across a wide range of system supply voltages, and also helps protect the device against common-mode power surges. refer to the applications section for help on calculating the r d resis- tance value. system enables there are several enabling inputs, which allow a host system to control the smh4812. the pin detect pins (pd1# & pd2#) are two active low enables that are generally used to indicate that the add-in circuit card is properly seated. this is typically done by clamping the inputs to v ss through the implementation of an injector switch, or alternatively through the use of a staggered pins at the card-cage interface. two shorter pins arrayed at opposite ends of the connector force the card to be fully seated (not canted) before both pin detects are enabled. care must be taken not to exceed the maximum voltage rating of these pins during the insertion process. refer to details in the applications section for proper circuit imple- mentation. the en/ts input provides an active high comparator input that may be used as a master enable or temperature sense input. these inputs must be held low for a period of t pdd before a power-up sequence may be initiated. under-/over-voltage sensing the under-voltage (uv) and over-voltage (ov) inputs provide a set of comparators that act in conjunction with an external resistive divider ladder to sense when the host supply voltage exceeds the user defined limits. if the input to the uv pin rises above 2.5v, or the input to the ov pin falls below 2.5v for a period of t pdd , the power-up se- quence may be initiated. the t pdd filter helps prevent spurious start-up sequences while the card is being in- serted. if uv falls below 2.5v or ov rises above 2.5v, the pg and vgate outputs will be shut down immediately. under-/over-voltage filtering the smh4812 may also be configured so that an out of tolerance condition on uv/ov will not shut off the output immediately. instead, a filter delay may be inserted so that only sustained under-voltage or over-voltage conditions will shut off the output. when the uv/ov filter option is enabled an out of tolerance condition on uv/ov for longer than the filter delay time, t uofltr , activates the fault# output, and the vgate and pg outputs will be latched in the off state. see figure 1. to initiate another power-up sequence the fault# output must first be reset. refer to the appropriate section on resetting the fault# output. the under-/over-voltage filtering feature is disabled in the default configuration of the device.
8 smh4812 2055 4.1 03/27/09 summit microelectronics, inc. preliminary figure 3. power on timing sequence figure 2. circuit breaker cycle mode figure 1. under-/over-voltage filter timing 2055 fig03 v dd uv ov pd1#/ pd2# vgate drain sense 2.5v ref 2.5v ref 11 v dd 13 t pdd pg# 9 2055 4.1 03/27 /09 smh4812 summit microelectronics, inc. preliminary under-voltage hysteresis the under-voltage comparator input may be configured with a programmable level of hysteresis. the compare level may be set in steps (up to 15) of 62.5mv below 2.5v. the default under-voltage hysteresis level is set to 62.5mv. soft start slew rate control once all of the preconditions for powering up the dc/dc controllers have been met, the smh4812 provides a means to soft start the external power fet. it is important to limit in-rush current to prevent damage to the add-in card or disruptions to the host power supply. for example, charging the filter capacitance (normally required at the input of the dc/dc controllers) too quickly may generate very high current. the vgate output of the smh4812 is current limited to i vgate , allowing the slew rate to be easily modified using external passive components. the slew rate may be found by dividing i vgate by the gate-to-drain capacitance placed on the external fet. a complete design example is given in the applications section. load control ? sequencing the secondary sup- plies once power has been ramped to the dc/dc controllers, two conditions must be met before the pg# output can be enabled: the drain sense voltage must be below 2.5v, and the vgate voltage must be greater than v dd ? v gt . the drain sense input helps ensure that the power mos- fet is not absorbing too much steady state power from operating at a high v ds . this sensor remains active at all times (except during the current regulation period). the vgate sensor makes sure that the power mosfet is operating well into its saturation region before allowing the loads to be switched on. once vgate reaches v dd ? v gt this sensor is latched. when the external mosfet is properly switched on the pg# output may be enabled (if enpg is high). output pg# is activated after a t pgd delay. the delay time is program- mable from 50s to 160ms. the pg# output has a 12v withstand capability, so high voltages must not be connected to this pin. a bipolar transistor or an opto-isolator can be used to boost the withstand voltage to that of the host supply. see figure 9 for connections. forced shutdown ? secondary feedback the forced shutdown signal (fs#) is an active low input that provides a method of receiving feedback from the secondary side of the dc/dc controllers. a built-in holdoff timer allows the smh4812 to ignore the state of the fs# input until the timer period expires. the fs# input must be driven high by the end of this timer period. a low level on this input will cause a fault condition, driving fault# low and shutting off the vgate and pg# outputs. the purpose of the holdoff timer is to allow enough time for devices on the secondary side of the dc/dc controllers to power up and stabilize. this unique feature of the smh4812 allows supervisory circuits such as an sms44 to control the shutdown of the primary side soft start circuit, even though the secondary side initially has no power. the fs# input can be programmed to act as a second enpg input controlling the pg# output. circuit breaker operation the smh4812 provides a number of circuit breaker func- tions to protect against over current conditions. a sus- tained over-current event could damage the host supply and/or the load circuitry. the board ? s load current passes through a series resistor (r s ) connected between the mosfet source (which is tied to cbsense) and v ss . the breaker trips whenever the voltage drop across r s is greater than 50mv for more than t cbd (a programmable filter delay ranging from 10s to 500s). quick-trip tm circuit breaker additionally, the smh4812 provides a quick-trip feature that will cause the circuit breaker to trip immediately if the voltage drop across r s exceeds v qcb . the quick-trip level may be set to 60mv, 100mv (default), 200mv, or the feature may be disabled. 2055 fig04 cbsense vgate 10 smh4812 2055 4.1 03/27 /09 summit microelectronics, inc. preliminary current regulation the current regulation mode is an optional feature that provides a means to regulate current through the mos- fet for a programmable period of time. see figures 5a and 5b. if enabled the device will start the internal timer when the voltage at cbsense exceeds 50mv (a & g, h). also, it attempts to limit the voltage at cbsense to 60mv by regulating the vgate output (b & c vs. i). the circuit breaker will trip if the over-current condition remains after the time-out (d, e, f; & j, k, l). however, if cbsense drops below 50mv before the timer ends, the timer is reset and vgate resumes normal operation. if the quick-trip level is exceeded then the device will bypass the current regulation timer and shut down immediately. the current regulation feature is disabled in the default configuration. non-volatile fault latch the smh4812 also provides an optional nonvolatile fault latch (nvfl) circuit breaker feature. the nonvolatile fault latch essentially provides a programmable fuse on the circuit breaker. when enabled the nonvolatile fault latch will be set whenever the circuit breaker trips. once set, it cannot be reset by cycling power. n ote : t he device remains permanently disabled until it is reprogrammed at the factory . as long as the nvfl is set, the fault# output will be driven active. the non-volatile fault latch feature is disabled in the default configuration. resetting fault# when the circuit breaker trips the vgate output is turned off and fault# is driven low. in the default condition the breaker resets automatically after a time of t cyc . in the latched condition cycling power to the board or toggling the en/ts input will also reset the circuit breaker. if the over current condition still exists after the mosfet switches back on, the circuit breaker will re-trip. figure 5.a. current regulation & shutdown figure 5.b. current regulation & shutdown vgate 0v 0v fault# cbsense 50mv 12v 1 0 a d c b e f 2055 fig05a vgate 0v 0v fault# cbsense 50mv 12v 1 0 g j h k i l 2055 fig05b
11 2055 4.1 03/27/09 smh4812 summit microelectronics, inc. preliminary applications operating at high voltages the breakdown voltage of the external active and passive components limits the maximum operating voltage of the smh4812 hot-swap controller. components that must be able to withstand the full supply voltage are: the input and output decoupling capacitors, the protection diode in se- ries with the drain sense pin, the power mosfet switch and the capacitor connected between its drain and gate, the high-voltage transistors connected to the power good outputs, and the dropper resistor connected to the controller ? s v dd pin. over-voltage and under-voltage resistors in the following examples, the three resistors, r1, r2, and r3, connected to the ov and uv inputs, must be capable of withstanding the maximum supply voltage of several hundred volts. the trip voltage of the uv and ov inputs is 2.5v relative to v ss . as the input impedance of uv and ov is very high, large value resistors can be used in the resistive divider. the divider resistors should be high stability, 1% metal-film resistors to keep the under-voltage and over-voltage trip points accurate. telecom design example a hot-swap telecom application may use a 48v power supply with a ? 25% to +50% tolerance ( i.e. , the 48v supply can vary from 36v to 72v). the formulae for calculating r1, r2, and r3 follow. first a peak current, id max , must be specified for the resistive network. the value of the current is arbitrary, but it can't be to high (self-heating in r3 will become a problem), or too low (the value of r3 becomes very large, and r3 becomes very expensive). to set the calculations a nominal value of 250a will be assumed. with v ov (2.5v) being the over-voltage trip point, r1 is calculated by the formula: ov max v r1 id = ==? = == ? = ? ==? ? () += =? =??=???=? ? = +
12 smh4812 2055 4.1 03/27 /09 summit microelectronics, inc. preliminary the min/max current limits are easily met using the drop- per resistor, except in circumstances where the input voltage may swing over a very wide range ( e.g. , input varies between 20v and 100v). in these circumstances it may be necessary to add an 11v zener diode between v dd and v ss to handle the wide current range. the zener voltage should be below the nominal regulation voltage of the smh4812 so that it becomes the primary regulator. mosfet v ds (on) threshold the drain sense input on the smh4812 monitors the voltage at the drain of the external power mosfet switch with respect to v ss . when the mosfet ? s v ds is below the user-defined threshold the mosfet switch is considered to be on. the v ds (on) threshold is adjusted using the resistor, r t , in series with the drain sense protection diode. this protection, or blocking, diode prevents high voltage breakdown of the drain sense input when the mosfet switch is off. a low leakage mmbd1401 diode offers protection up to 100v. for high voltage applications (up to 500v) the central semiconductor cmr1f-10m diode should be used. the v ds (on) threshold is calcu- lated from: () ( ) =?? ? () ( ) =? ??= () =+ ? ?
13 2055 4.1 03/27 /09 smh4812 summit microelectronics, inc. preliminary applications circuits figure 6. changing polarity of power good output (pg#) 2.5v ref r t 68k 1k *10 10nf 100v mmbd1401 100nf mmbta- 06lt1 100nf 50v 100nf 50v 10nf 100v uv ov pd1# pd2# fault# v dd enpg 5v ref smh4812 pg# v ss cbsense v gate drain sense 0v ? 48v 10k 10k r1 r d 6.8k 100f 100v r3 r2 r s 20m 47k mmbd- 1401 0v ? 48v 2055 fig06 fs# en/ts note: figures 6 through 9 ? the *10 resistor must be located as close as possible to the mosfet
14 smh4812 2055 4.1 03/27 /09 summit microelectronics, inc. preliminary figure 7. overtemperature shutdown r t 68k 1k *10 10nf 100v mmbd1401 100nf 100k mmbta06lt1 100nf 50v 100nf 50v 10nf 100v uv ov pd1# pd2# fault# v dd enpg pg# 5v ref smh4812 v ss cbsense v gate drain sense 0v ? 48v 10k 10k r1 r d 6.8k 100f 100v r3 1m r2 r s 20m 0v ? 48v 2.5v ref en/ts + ? lmv331 1k 50k ntc 50k @t max 100nf 50v 2055 fig07 fs# note: figures 6 through 9 ? the *10 resistor must be located as close as possible to the mosfet
15 2055 4.1 03/27 /09 smh4812 summit microelectronics, inc. preliminary figure 8. expanding input monitoring capability r t 68k 1k *10 10nf 100v mmbd1401 100nf 100k mmbta06lt1 100nf 50v 100nf 50v 10nf 100v uv ov pd1# pd2# fault# v dd enpg pg# 5v ref smh4812 v ss cbsense v gate drain sense 0v ? 48v 10k 10k r1 r d 6.8k 100f 100v r3 1m r2 r s 20m 0v ? 48v 2.5v ref en/ts 1k 100nf 50v + ? lmv 339 + ? + ? + ? en1 en4 en2 en3 10k 2055 fig08 fs#
16 smh4812 2055 4.1 03/27 /09 summit microelectronics, inc. preliminary figure 9. typical application for dc/dc converter note: figures 6 through 9 ? the *10 resistor must be located as close as possible to the mosfet 68k 1k *10 10nf 100v mmbd1401 100nf 100k mmbta06lt1 0v ? 48v +vin ? vin on/off +vout ? vout uv ov pd1# pd2# v dd pg2# 5v ref smh4812 v ss cbsense v gate drain sense 10k 10k r3 r2 r s r1 r d 6.8k 0v 100nf 50v 2055 fig09 dc / dc converter with active low on/off control 10nf 100v 100f 100v 100nf 50v enpg fs# fault# v en/ts
17 smh4812 2055 4.1 03/27 /09 summit microelectronics, inc. preliminary 16 pin soic package note: 1. reference: jedec publication ms-012 ptx 360-120 2. unit: inches 3. mold flash, protrusion & gate burr shall not exceed 0.006 inch per side. .016 .002 155 0.005 .0085 .0010 (after plating) 0 8 45 1 0.024 0.002 0.054 0.005 0.007 0.003 0.023 0.005 detail a detail a 0.041 0.069 max 0.151 0.005 0.05 bsc pin 1 index 0.016 0.003 0.1550.005 9 16 8 1 0.236 0.008 0.390 0.005 soic 16 0.390 0.005 .007 .003 .004 7 1 7 1 7 1 2055 soic 1.0
18 2055 4.1 03/27 /09 smh4812 summit microelectronics, inc. preliminary notice summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user ? s specific application. while the information in this publication has been carefully checked, summit microelectronics, inc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. this document supersedes all previous versions. ? copyright 2000 summit microelectronics, inc. ordering information smh4812 s base part number package s = soic 2055 tree 1.0

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